The SAFEPROCESS TC promotes on-line fault and cyber-attack detection, isolation, estimation, and diagnosis, with a view to predictive maintenance and supervision, as well as fault tolerant and cyber-secure control. It addresses residual generation, residual evaluation, performance monitoring, statistical hypothesis testing, on-line change detection, software sensors, active input signal generation for FDI, decision making, controller reconfiguration and switching, accommodation against cyber-attacks. It relies on system theory, statistics, system identification, statistical process control, artificial intelligence and optimization theory. Processes described by models qualified as linear/ non-linear, uncertain, hybrid, lumped/ distributed parameters, rule-based and discrete-event models are considered. This TC also promotes analysis tools such as failure mode and effects analysis, severity analysis and reliability theory to achieve fault tolerant designs.